Performance, degradation and defect structure of MOS devices using high-k materials as gate dielectrics

Completed

Energy Efficiency(Other)

Basic and strategic applied research

ENGINEERING AND TECHNOLOGY (Electrical and Electronic Engineering)

Not Cross-cutting

Professor J Zhang
Engineering
Liverpool John Moores University

Standard

EPSRC

01 February 2005

31 March 2008

38 months

£191,097

Info. & commun. Technol.

North West

Information & Communication Technology

Professor J Zhang, Engineering, Liverpool John Moores University

Project Contact, NMRC - National Microelectronics Research Centre, Ireland
Project Contact, Imperial College London
Project Contact, University of Glasgow
Project Contact, University Centre Peterborough
Project Contact, University Centre Somerset
Project Contact, International SEMATECH, USA
Project Contact, IMEC, Belgium

The transistors in successive generations of integrated circuits have increased in speed, use less power and cost less because of diminishing transistor sizes. Unfortunately, it is not possible to reduce the operating voltage with the same scaling factors as the physical size so the electric fields in the transistor have increased dramatically. The silicon dioxide which is used as the gate of these transistors is now so thin that a significant current flows through this insulating layer at normal operating voltages because of tunnelling. This increases power consumption and reduces reliability. Future transistor generations will need a gate dielectric of higher permittivity (high-k) that will allow a larger physical thickness to be used without increasing the equivalent electrical thickness. This is the most important single issue facing the development of integrated circuits at the moment. The high-k materials proposed by the industry (materials based on hafnium oxide are favouredat the moment) are physically and chemically very different to silicon dioxide. Considering the importance of this technological leap surprisingly little is known about their interface characteristics with silicon or about the trapping sites in the oxide. In this research programme three NW Universities will collaborate with IMEC in Belgium, SEMATECH in the USA, NMRC in Ireland, Imperial College and Glasgow University to achieve an understanding of the underlying science of these gate dielectrics. This will be done by applying both novel research tools and industry standard methods to analyse the interface and bulk trapping centres and to observe their evolution under electrical stress. A key issue will be the role of hydrogen and deuterium in these materials and the physical and electronic structure of the traps

01/01/07